The present invention relates to a phase-locked loop circuit comprising in sequential connection: a digital phase comparator, to one input of which a reference frequency is supplied; a loop filter; and a voltage-controlled oscillator, from which a feedback branch is connected to the second input of the phase comparator.
A block diagram of a phase-locked loop is shown in FIG. 1. In the figure, the reference frequency Fref is applied to the input of the phase comparator. The output of the phase comparator is connected to the loop filter 2. The loop filter (2) output is applied to the voltage-controlled oscillator 3. The output of the oscillator 3 is fed back to the phase comparator 1 so as to provide a loop that is locked according to the reference frequency Fref at a certain rate.
It is well known in the art to use a phase-locked loop in frequency synthesizers. When a phase-locked loop is used in a frequency synthesizer, the frequency modulated voltage-controlled oscillator (VCO) imposes, contradictory loop bandwidth requirements. A rapid locking time is desired for channel switching thus requiring, the loop bandwidth to be as high as possible. On the other hand, for the loop not to accentuate nor to damp the frequency modulation, its bandwidth should be far lower than the lowest modulation frequency. A low loop bandwidth also reduces residual modulation and increases the damping of the phase reference frequency.
U.S. Pat. Nos. 4,482,869 and 4,516,083, for instance, and EP patent application 85615 disclose an acceleration of the loop filter by changing the resistance value of the integrator stage of the filter by either removing resistors or by short circuiting them. Correspondingly, the retardation is achieved by removing the short-circuits or adding resistors. In U.S. Pat. No. 4,156,855 the loop is additionally accelerated by using a current pump to increase the current feeding the integrator stage capacitor.
Controlling the resistors with switches, however, disturbs the operation of the loop. Thus, at the moment of switching resistors in a slow loop, a momentary spike usually appears in the adjusting voltage obtained from the VCO, which is inadmissible for some applications, for example radiotelephones. The same happens in the case of a sudden change of the current charging the integrator.
Consequently, a frequency synthesizer formed by a phase-locked loop has been impossible to use without drawbacks where, a rapid locking time or a linear modulation frequency response is required. In cases where a modulated frequency synthesizer is formed by a phase-locked loop there have been compromises between the locking time, the linearity of the modulation frequency response, and the reference frequency damping.
For example, in radiotelephone applications requiring a short locking time and a linear modulation frequency response, it has been necessary to use a so-called transfer oscillator system, in which a modulated fixed transfer oscillator frequency is mixed with the receiver injection frequency. On the other hand, a transfer oscillator has the drawbacks of producing a great number of mixing results, which are difficult to damp and complicated and expensive circuitry.